SpeedSim/3

SpeedSim/3



Performance:

  • 10 to 100 times faster that Chronologic VCS or MTI!
  • 100 to 2,000 cycles per second throughput on large designs

    Language Support:

  • Verilog Support at both RTL and GATE levels
  • Behavioural test-benches with PLI Support

    SMP and ST:

  • Up to 32 test-benches running in parallel (ST)
  • Linear gain with up to 8 processors (SMP)

    Muliti-Platform:

  • Sun Sparc, HP, IBM, NT
  • Minimul memory requirements (1/5th Chronologic)

    Reducing the time and cost of design verification...

  • Interested, visit the SpeedSim Home Page